In this paper, we present a novel cache design based on Multi-Level CellSpin-Transfer Torque RAM (MLC STTRAM) that can dynamically adapt the setcapacity and associativity to use efficiently the full potential of MLC STTRAM.We exploit the asymmetric nature of the MLC storage scheme to build cache linesfeaturing heterogeneous performances, that is, half of the cache lines areread-friendly, while the other is write-friendly. Furthermore, we propose toopportunistically deactivate ways in underutilized sets to convert MLC toSingle-Level Cell (SLC) mode, which features overall better performance andlifetime. Our ultimate goal is to build a cache architecture that combines thecapacity advantages of MLC and performance/energy advantages of SLC. Ourexperiments show an improvement of 43% in total numbers of conflict misses, 27%in memory access latency, 12% in system performance, and 26% in LLC accessenergy, with a slight degradation in cache lifetime (about 7%) compared to anSLC cache.
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